1. Field of the Invention
The present invention relates to a method of driving a matrix display type plasma display panel (hereinafter referred to as PDP).
2. Description of Related Art
As well known, PDP has been variously studied as a thin planar display device. A matrix display type PDP is known as one of the PDPs.
As one of methods of displaying an image with gradation on this matrix display type PDP, known is a so-called subfield method in which the image is displayed by dividing one field of display period into N subfields to be lighted for a period of time corresponding to weighted bit positions of N-bit pixel data.
This subfield method comprises the steps of: simultaneous reset for once initializing all of discharge cells; address writing for setting lighting discharge cells and un-lighting discharge cells by scanning an address (writing the data) in accordance with image data; and sustain discharge for holding the lighting discharge cells and un- lighting discharge cells discharged by the application of a sustain pulse.
At this time, a cycle of the address write must be shortened in order to realize a highly fine display by increasing the number of lines and increasing the number of display gradation in such a PDP.
For example, when the image is displayed at VGA resolution of 640.times.480 dots, 4-5 [.mu.SEC] are satisfactory for a scan rate. However, the higher-speed write, for example, a write period of about 2 [.mu.SEC] is required to display the image at XGA resolution of 1024.times.768 dots.
FIG. 1 shows a configuration of a plasma display device for carrying out such a high-speed address write.
In PDP 10 shown in FIG. 1, formed are row electrodes Y.sub.1 -Y.sub.4 and row electrodes X.sub.1 -X.sub.4 which make pairs of row electrodes so that a pair of X and Y may correspond to each of rows (the first to fourth rows) on one screen. Furthermore, formed are column electrodes D.sub.1 -D.sub.4 which make column electrodes so that they may be perpendicular to these pairs of row electrodes, a dielectric layer and a discharge space (not shown) may be placed therebetween and they may each correspond to each of columns (the first to fourth columns) on one screen. At this time, one discharge cell is formed at an intersection of a pair of row electrodes (X, Y) and one column electrode D.
An address driver 20 converts one screen of pixel data in the PDP 10 into pixel data pulses corresponding to these pixel data on a row-by-row basis. These pulses are applied to each of the address electrodes D.sub.1 -D.sub.4 in an order as shown in FIGS. 2A-2G:
a pixel data pulse group DP.sub.1 corresponding to the first row;
a pixel data pulse group DP.sub.3 corresponding to the third row;
a pixel data pulse group DP.sub.2 corresponding to the second row; and
a pixel data pulse group DP.sub.4 corresponding to the fourth row.
Here, an X-row electrode driver 30 first applies a reset pulse RP.sub.X as shown in FIG. 2B to the row electrodes X.sub.1 -X.sub.4.
A Y-row electrode driver 40A is used for applying various driving pulses as described below to a block of the row electrodes Y in the upper half of one screen in the PDP 10,that is, the row electrodes Y.sub.1 and Y.sub.2. On the other hand, a Y-row electrode driver 40B is used for applying various driving pulses as described below to a block of the row electrodes Y in the lower half of one screen in the PDP 10, that is, the row electrodes Y.sub.3 and Y.sub.4.
In FIGS. 2C through 2F, at the same time when the reset pulse RP.sub.X is applied to the row electrodes, the Y-row electrode driver 40A applies a reset pulse RP.sub.Y as shown in FIGS. 2C and 2D to the row electrodes Y.sub.1 and Y.sub.2. Moreover, at the same time when the reset pulse RP.sub.X is applied to the row electrodes, the Y-row electrode driver 40B applies a reset pulse RP.sub.Y as shown in FIGS. 2E and 2F to the row electrodes Y.sub.3 and Y.sub.4 (a reset step).
This application of the reset pulse causes all the discharge cells in the PDP 10 to be discharged/excited, so that charged particles are generated. After the termination of this discharge, a predetermined amount of wall charges are uniformly formed on the dielectric layers in all the discharge cells.
Next, immediately after applying a positive-voltage priming pulse as shown in FIG. 2C to the row electrode Y.sub.1, the Y-row electrode driver 40A applies a negative-voltage scan pulse SP to the row electrode Y.sub.1. At this time, immediately after applying the positive-voltage priming pulse to the row electrode Y.sub.3 at a timing as shown in FIG. 2E, the Y-row electrode driver 40B applies the negative-voltage scan pulse SP to the row electrode Y.sub.3. Furthermore, immediately after applying the positive-voltage priming pulse to the row electrode Y.sub.2 at a timing as shown in FIG. 2D, the Y-row electrode driver 40A applies the negative-voltage scan pulse SP to the row electrode Y.sub.2.
Furthermore, immediately after applying the positive-voltage priming pulse to the row electrode Y.sub.4 at a timing as shown in FIG. 2F, the Y-row electrode driver 40B applies the negative-voltage scan pulse SP to the row electrode Y.sub.4 (an address step).
At this time, out of the same cells existing in the row electrodes to which the scan pulse SP has been applied, the discharge occurs in the discharge cells to which the high-voltage pixel data pulse DP has been applied, most of the wall charges are thus lost. On the other hand, since no discharge occurs in the discharge cells to which the low-voltage pixel data pulse DP has been applied, the wall charges remain. That is, executed is a so-called pixel data write in which whether or not the wall charges remain in the discharge cells is determined depending on the pixel data pulse DP applied to the column electrode.
A priming pulse PP is applied to the electrode immediately before the application of the scan pulse, whereby the charged particles, that have been obtained in the above-described reset step and reduced as time has passed, are reformed in the discharge space in the PDP.
Therefore, under the same conditions in which these charged particles are present on any one of the first to fourth rows, the pixel data write by the application of the scan pulse SP is carried out.
Next, the X-row electrode driver 30 incessantly applies a positive-voltage sustain pulse IP.sub.X to the row electrodes X.sub.1 -X.sub.4. The Y-row electrode drivers 40A and 40B incessantly apply a positive-voltage sustain pulse IP.sub.Y to the row electrodes Y.sub.1 -Y.sub.4 at a timing shifted from the timing of the application of the sustain pulse IP.sub.X (a sustain discharge step).
Over the time period for which the sustain pulses IP.sub.X and IP.sub.Y are alternately applied to the row electrodes, the discharge cells in which the above-mentioned wall charges remain are repeatedly discharged and emit a light, and the discharge cells keep emitting the light.
As described above, in such a driving method, an attempt is made to reduce an address write cycle by overlapping the timing of the application of the priming pulse PP with the timing of the application of the scan pulse SP to other row electrodes.
For example, when a write scan (addressing) is performed for the row electrode Y.sub.1 on the first row, the negative-polarity scan pulse SP applied to this row electrode Y.sub.1, the positive-polarity pixel data pulse DP.sub.1 applied to the column electrodes D.sub.1 -D.sub.4 and the positive-polarity priming pulse PP applied to the row electrode Y.sub.3 on the third row of a second row electrode group (the row electrodes Y.sub.3 and Y.sub.4) are applied to the electrodes at an overlapping timing.
However, when the timings of the application of the pixel data pulse DP.sub.1 and the priming pulse PP are thus overlapped with each other, the negative wall charges are stored in the column electrodes D.sub.1 -D.sub.4 during a priming discharge by the priming pulse PP applied to the above-described row electrode Y.sub.3.
Therefore, in the write scan on the third row following this priming discharge, the negative-polarity scan pulse SP is applied to the row electrode Y.sub.3, whereby, during attempting to generate a selective erasure discharge responding to the positive-polarity pixel data pulse DP.sub.3, the selective erasure discharge is difficult to generate by an influence of the negative wall charges on the column electrodes D.sub.1 -D.sub.4 stored due to the just previous priming discharge, which makes a stable display operation difficult.
Moreover, when the waveform of each driving pulse to be applied to the aforementioned first row electrode group is caused to differ from the waveform of each driving pulse to be applied to the second row electrode group, the Y-row electrode drivers 40A and 40B become also disadvantageously unbalanced at the address margins thereof.